1. Field of the Invention
The present invention relates to electronic circuits and, more specifically, to a system for biasing body voltages in a silicon on insulator circuit.
2. Description of the Prior Art
In electronic semiconductors, silicon-on-insulator (SOI) structure is a technique for isolating complementary MOS (CMOS) transistors from a substrate. The principle is to establish a layer of insulating material (in general a silicon dioxide layer) not far away from the surface of a silicon substrate, thereby isolating a layer of substrate silicon from the main substrate body below. A CMOS transistor can then be fabricated on the isolated substrate silicon layer above the insulating layer, and hence the structure is called silicon-on-insulator. Since the area for fabricating the CMOS transistor is isolated from the substrate main body, certain conventional latch-up paths will be excluded. For example, conventional latch-up paths such as xe2x80x9csource terminal to the substratexe2x80x9d and xe2x80x9cwell region to the substratexe2x80x9d no longer exist due to the isolation provided by this insulating layer. SOI CMOS devices often operate at higher speeds than do bulk CMOS devices. SOI CMOS architecture eliminates inherent parasitic circuit elements in bulk CMOS due to junction capacitances between adjacent components.
SOI devices are characterized by a thin layer of insulating material, also referred to as a buried oxide layer, that is sandwiched between a bulk substrate and the circuit elements of the device. Typically, no other layers of material are interposed between the SOI and the bulk substrate. In an SOI CMOS device, the circuit elements above the SOI are established by regions of a field oxide semiconductive layer which are doped as appropriate with N-type or P-type conductivity dopants. For example, for an N channel transistor, the field oxide layer will include a gate element disposed over a body region having a P-type dopant, with the body region being disposed between a source region and a drain region, each of which are doped with an N-type dopant.
The SOI structure can be fabricated using isolation by implanted oxygen (SIMOX) method, bonded wafer method or dielectric isolation (DI) method. The advantages of having a SOI structure, other than being capable of reducing parasitic bipolar effects of a CMOS transistor, include the ability to increase its immunity to soft errors caused by powerful alpha.-particles. Furthermore, since the permitted line width is smaller, the level of integration can be increased. In addition, since the number of masks necessary for fabricating a device for a SOI structure is fewer, the manufacturing process is very much simplified. The reduction of parasitic bipolar effects together with the reduction of device dimensions further boost the operational speed of the circuit.
In one illustrative example of an SOI device, an active device region is defined out of a silicon main body by a device isolating structure. A buried oxide layer is formed in the silicon main body and a P-type silicon substrate is formed above the buried oxide layer. Then a gate terminal, for example, of a MOS transistor, is formed above the P-type silicon substrate. Finally, N-type source region and drain region are formed on each side of the gate terminal.
In such an SOI device, the P-type silicon substrate is in a floating state. Therefore, unwanted current can easily flow between the drain region and the source region due to the transfer of electrons at the interface between the source region and the P-type silicon substrate. This is the so-called floating body effect, which affects the functionality of the device as well as lowering its reliability. Hence, a tie down voltage is often connected to the P-type silicon substrate in order to reduce the floating body effect. To accomplish this, an extension area is added above the SOI device region. There is usually a contact window above the extension area for supplying the necessary low tie down voltage to the P-type silicon substrate.
Complementary metal oxide semiconductor (CMOS) devices that are produced in mass quantities are referred to as xe2x80x9cbulkxe2x80x9d CMOS, because they include a semiconductive bulk substrate on which active or passive circuit elements are disposed. Recently, SOI CMOS devices have been introduced which consume less power than do bulk CMOS devices. Analog circuits require close matching to perform properly. With the move to SOI processes to gain speed and lower power, typical SOI circuits employ body contacts to minimize tracking error between devices that need to match.
Another technique used to minimize tracking error is to employ long channel devices. However, as SOI technology shrinks below 0.13 micron, SOI long channel devices become fully depleted. This causes an dramatic increase in body resistance, which decreases the effect of the body contact and increases tracking error. To make a body contact have a low resistance in these shrunken technologies, the channels are highly doped. This raises the gate-source threshold voltage (VT) of the device, which causes power supply headroom problems in stacked circuits (which are prevalent in Analog circuit designs), thereby increasing noise variation.
Therefore, there is a need for a device that biases body voltages of silicon-on-insulator transistors to maintain the gate-source threshold voltages of the transistors within a predetermined range of a desired gate-source threshold voltage.
The invention biases the body voltages in SOI transistors to control VT and, thus, the gate-source voltage while using the gate-source voltage as feedback for devices. The invention improves matching and power supply headroom performance in analog and other circuits.
The disadvantages of the prior art are overcome by the present invention which, in one aspect, is an apparatus for biasing a body voltage of a silicon-on-insulator transistor having a gate and a body. An operational amplifier senses a voltage difference between a desired gate-source threshold voltage and a reference voltage at a reference current source node and generates an output voltage that is proportional to the voltage difference. A reference biasing transistor has a gate that is electrically coupled to the output voltage and has a drain. A reference mirror transistor has both a gate and a drain that are electrically coupled to the current source node. The reference mirror transistor also has a body that is electrically coupled to the drain of the reference biasing transistor. A device biasing transistor has a gate that is electrically coupled to the output voltage and has a drain that is electrically coupled to the body of the silicon-on-insulator transistor. The device biasing transistor maintains a voltage at the body of the silicon-on-insulator transistor so that the silicon-on-insulator transistor has a gate-source threshold voltage that is within a predetermined range of the desired gate-source threshold voltage.
In another aspect, the invention is an apparatus for biasing a device body so as to maintain a desired gate-source threshold voltage of a device. The device has a device gate, a device source, a device drain and a device body. The device also has a device gate-source threshold voltage. The device is driven by a reference current from a reference current node, which has a reference voltage. An operational amplifier is capable of generating an output voltage that is proportional to a voltage difference between the desired gate-source threshold voltage and the reference voltage. The operational amplifier has a first input and a second input. The first input is electrically coupled to the desired gate-source threshold voltage and the second input is electrically coupled to the reference current node.
At least two body biasing transistors, including a first body biasing transistor and a second body biasing transistor, each have a biasing transistor drain and a biasing transistor gate that is driven by the output voltage of the operational amplifier. Each of the body biasing transistors is capable of supplying a body biasing current that is proportional to the output voltage. The biasing transistor drain of the second body biasing transistor is electrically coupled to the device body. A reference transistor has a reference gate, a reference source, a reference drain and a reference body. The reference drain and the reference gate are electrically coupled to the reference current node. The reference body is electrically coupled to the body biasing drain of the first body biasing transistor. A first passive component is electrically coupled to the reference body and causes the reference body to have a reference body voltage that is proportional to the body biasing current so that the reference voltage is within a predetermined range of the desired gate-source threshold voltage. A second passive component is electrically coupled to the device body and causes the body to have a body voltage that is proportional to the body biasing current so that the device gate-source threshold voltage is within the predetermined range of the desired gate-source threshold voltage.
In yet another aspect, the invention is a method of biasing a body voltage of a device having a device gate-source threshold voltage. A voltage difference is sensed between a desired gate-source threshold voltage reference and a node voltage of a reference drain of a reference transistor, where the reference drain is electrically coupled to a reference gate of the reference transistor. A biasing current that is proportional to the voltage difference is sourced. A body biasing voltage that is proportional to the biasing current is generated and drives the body voltage of the device so that the device gate-source threshold voltage is within a predetermined range of the desired gate-source threshold voltage.
The embodiment disclosed herein is a current mirror. However the invention can be used in a wide variety of circuits.
These and other aspects of the invention will become apparent from the following description of the preferred embodiments taken in conjunction with the following drawings. As would be obvious to one skilled in the art, many variations and modifications of the invention may be effected without departing from the spirit and scope of the novel concepts of the disclosure.